The present invention relates to a thin film wiring board with a via used for interlayer connection. More particularly, this invention relates to the thin film wiring board that allows manufacturing yield to be improved and a method for manufacturing the thin film wiring board. Further, this invention relates to a method for correcting a void defect occurring on the surface of a base substrate used for the thin film wiring board.
In recent years, a multilayer thin film wiring board that enables high density wiring on an MCM (Multi Chip Module) board or the like has been in the actual use, and applied in electronic equipment such as a computer. This multilayer thin film wiring board is provided by laminating an insulating layer and a wiring layer. The insulating layer is generally made of polyimide and formed to be extremely thin by spin-coating. A high-density pattern is also formed on the wiring layer by using sputtering and a highly sensitive resist.
This multilayer thin film wiring board has a structure that allows the wiring and the power supply between electronic components by connecting LSI (Large Scale Integrated Circuit) packed on the surface of the board and terminals (signal terminal, power terminal, and ground terminal) of the electronic components such as input/output pins to a desired layer through vias.
In recent years, the multilayer thin film wiring board is also becoming denser in association with tighter packing of LSIs. Accordingly, at present, surface defects may easily be generated in the manufacturing process of the multilayer thin film wiring board, and reduction in the yield becomes an issue that should be taken care of. An effective solution to this problem is eagerly expected.
FIG. 10 and FIG. 11 show general views of the MCM. As shown in FIG. 10, a plurality of LSI chips 69 are mounted on the thin film wiring board 68, and cooling fins 71 for cooling are mounted above the chips. The input/output pins 70 for connection with a mother board not shown are provided in the opposite side to the cooling fins 70 with the LSI chip 69 in between.
The thin film wiring board 68 is structured with a thin film layer 74 formed on a ceramic substrate 72 as shown in FIG. 11, and a connection between the thin film wiring board 68 and the LSI chip not shown is made by a soldering bump 75. The diameter of a via 73 provided in the ceramic substrate 72 is around 0.1 mm to 0.2 mm.
FIG. 12A to FIG. 12E show cross-sectional views of the structure and the manufacturing process of a conventional multilayer thin film wiring board. FIG. 12A shows a ceramic substrate 1 having vias 2a and 2b. This ceramic substrate 1 is obtained by sintering a laminated thin-film ceramic sheet, and the surface 1c of this ceramic substrate 1 is flattened. A surface defect 3a occurs due to the difference between the hardness of the ceramic substrate 1 and that of the via 2b. Further, the surface 1c of the ceramic substrate 1 is supposed to have irregularities due to a phenomenon that ceramic particles are detached or a phenomenon that voids occurring at the time of sintering the ceramic substrate 1 are exposed.
In the manufacturing process using the ceramic substrate 1 shown in FIG. 12A, a via connecting pad 4a and a via connecting pad 4b are formed on the surface 1c of the ceramic substrate 1 as shown in FIG. 12B by means of sputtering or the like. During this process, a protrusion 4c is formed on the via connecting pad 4a caused by dust or the like, and a defect 3b occurs in the via connecting pad 4b under the influence of the surface defect 3a (see FIG. 12A). In this state, a via 5a and a via 5b are formed so as to protrude upward on the respective surfaces of the via connecting pad 4a and the via connecting pad 4b, as shown in FIG. 12C.
In the next manufacturing process, a polyimide insulating layer 6 (see FIG. 12D) as an insulator is formed on the surface 1c of the ceramic substrate 1, and then the surface of the polyimide insulating layer 6 is polished as shown in FIG. 12D. At this time, the top section of the protrusion 4c is shaved and thus exposed, while a tapered defect 3d is formed due to a defect 3c (see FIG. 12C). Thus, the defective portion grows as follows: surface defect 3a xe2x86x92defect 3bxe2x86x92defect 3cxe2x86x92defect 3d as the manufacturing process proceeds along the steps of FIG. 12A to FIG. 12D.
In the next manufacturing process, patterns 7a to 7d are formed on the surface of the polyimide insulating layer 6 shown in FIG. 12E through the plating process, respectively. The pattern 7a and the via connecting pad 4a are short-circuited through the protrusion 4c, and in the same manner as explained above, the pattern 7c and the via connecting pad 4b are short-circuited through the protrusion 7e formed inside the defect 3d (see FIG. 12D). In the normal state, the pattern 7a has to be insulated from the via connecting pad 4a and the pattern 7c has to be insulated from the via connecting pad 4b as well. That is, the multilayer thin film wiring board shown in FIG. 12E is regarded as a defective.
By the way, the conventional multilayer thin film wiring board is manufactured through the manufacturing process steps as shown in FIG. 12B to FIG. 12E as explained above. However, during this process, a large number of defects may be generated because of the irregularities on the surface such as the surface defect 3a and the protrusion 4c. Accordingly, the manufacturing yield is reduced. This reduction of the yield may result in increase in cost of the multilayer thin film wiring board.
That is, the pattern 7a and the pattern 7b shown in FIG. 12E should originally be insulated from each other, but are short-circuited through the protrusion 4c, the via connecting pad 4a, and the via 5a. In the same manner as the above case, the pattern 7c and the pattern 7d should originally be insulated from each other, but are short-circuited through the protrusion 7e, the via connecting pad 4b, and the via 5b. 
Recently, as the number of LSI terminals is increasing due to its higher density, the number of lines of wiring on the board that connects between LSIs is increasing, thus finer pitches of the wiring are demanded. This demand is stronger particularly for the thin film wiring board used in an MCM board, therefore, finer pitches of the wiring are progressing. The conventional method for manufacturing the thin film wiring board is shown in FIG. 13A to FIG. 13G.
At step 1, the ceramic substrate is sliced (around 0.1 mm to 0.3 mm), and holes are punched in the substrate (FIG. 13A). Each of the holes is then filled with tungsten (W) 81 to form a thin green sheet 80 as shown in the figure. aluminum ceramic, ceramic of aluminum nitride, or glass ceramic are used as a material of the ceramic substrate, and tungsten 81 or molybdenum or the like is used as metal for conduction to be filled in the holes. When the material of the ceramic substrate is glass ceramic, copper (Cu) is also usable as metal for conduction to be filled in the holes.
At step 2, a plurality of the green sheets 80 are laminated, pressurized, and sintered to form a sheet of base substrate 72 (see FIG. 13B and FIG. 13D). At this time, the tungsten 81 filled in the holes at step 1 becomes a via 73 which allows interlayer electric conduction.
At step 3, the surface of the base substrate 72 is mechanically polished to flatten the irregularities of the surface (see FIG. 13C and FIG. 13E).
At step 4, a chrome (Cr) layer or a titanium (Ti) layer as contact metal and a copper layer as a current-carrying layer at the time of plating are formed by a sputtering method. (Hereafter these layers are referred to as conductor layer as under plating. See FIG. 13F).
At step 5, a layer of copper 86 is formed in desired thickness on the conductor layer 85 as under plating formed at the previous step by electroplating. By the use of photolithography copper is formed only a required location (see FIG. 13G).
At step 6, a sputtered layer 85 within an area where the layer of copper 86 has not been formed is removed by etching. Any solution with which etching is selectably executed on each metal is used may be used as the enchant.
From then on, a thin film layer is formed on the base substrate 72 to finish a thin film wiring board by the ordinary manufacturing method for forming a thin film layer.
The most significant problem on the manufacturing method for the thin film wiring board is existence of a pin hole (hereafter referred to as Void) with its diameter of several pm occurring in tungsten 81 forming a via.
The void 84 occurs mainly at the time of filling the via with tungsten 81 in the step of forming the green sheet 80. More specifically, there are cases where the void occurs: during the operation of making tungsten 81 to a paste form, and due to being short of tungsten during the operation of filling the via with the paste. The void 84, that has once occurred, remains inside the tungsten 81 as it is.
In some of thousands of vias 73, the voids 84 are exposed to the surface of the base substrate 72 after the polishing process as shown in FIG. 13D, which causes pits to be formed on the surface of the base substrate 72 that should be flat.
As explained above, the pits (hereafter referred to as Void defect) on the surface of the base substrate 72, that have been formed by exposure of the voids 84 to the surface of the base substrate 72, inhibit wiring formation on the thin film layer 74 (thin film multilayer circuit section) formed on the base substrate 72 in the process as follows.
For example, when a polyimide layer as an interlayer insulating layer is to be formed in the process of forming the thin film layer 74, a polyimide compound is applied in a spin coating method. However, if a conductive pattern is not formed on the via 73, the polyimide compound is directly applied onto the via. In that case, the polyimide compound has not thoroughly entered as far as the internal side of some of the void defects, resultantly, the void defect has a space with air in it.
In the following sintering process, expansion of the air brings about such a phenomenon that the polyimide is rejected. As a result, the polyimide layer as an insulating layer for upper and lower patterns disappears, so that the layer to be laminated on that location is formed defectively, or the conductive pattern to be laminated on that location is short-circuited with the via 73 existing immediately below the pattern.
Further, when an etchant enters into the internal side of a void defect and is left inside in the process of forming the thin film layer, corrosion to tungsten due to the etchant, that has entered into the internal side of the void defect, is progressing with time as shown in an erosion portion 87 of FIG. 13G (although there is no functional defect at the time of manufacturing the thin film wiring board), and a malfunction may occur after some years.
As explained above, a board having a functional defect (or that will have a functional defect in future) such as an open circuit in a conductive pattern or a short circuit between conductive patterns, and a board, on which the predetermined number of layers can not be built up due to formation defect of the thin film layer, can not be used as a product, thus being disposed. As a result, the manufacturing yield does not increase, which causes the cost of manufacturing the thin film wiring board to become high.
These problems may occur in the same mechanism as explained above even when the base substrate 72 is a resin board.
However, it is difficult to perfectly eliminate the voids, and there has been no effective means invented so far about the technology of avoiding formation defect of a thin film layer due to void defects that have occurred. Because the thin film layer is high density and multilayer, it is actually impossible to correct defective points after the thin film layer is formed.
In order to solve the problems, a method, that formation defect of a thin film layer may be minimized by filling avoid defect with some material, has been considered. It is the method for filling a void defect with the same type of metal as that of the via.
However, the surface of the base substrate is directly exposed to the etchant at the time of forming a thin film layer, therefore, it is essential that the recess due to the void defect is completely filled without any space left so that the etchant will not remain within the void defect.
In contrast to this, when a void defect is filled in any known method such as a squeegee method, it is difficult to completely fill such small void defects each of around several xcexcm without any void defect left and without any space left in each internal side. Further, the amount of the paste to be filled varies. Therefore, even if all the void defects are filled with the paste and the surface looks like a completely filled state, there may still be left some of the void defects in which the paste may be imperfectly filled in each internal side.
As a result, assuming that tungsten is used for correction, the surface of the corrected parts is directly exposed to the etchant at the time of etching. The tungsten has a property of being eroded by the etchant for chrome that is a conductor as under plating. Therefore, the surface portion is dissolved, and the etchant enters into the void defect portion imperfectly filled with the paste from the dissolved surface. Accordingly, the etchant is not completely removed and left inside the void defect portion even after the operation of removing the etchant from the void, which may derive inconvenience afterward.
It is an object of the present invention to provide a thin film wiring board that allows manufacturing yield to be improved and a method for manufacturing the thin film wiring board.
According to the present invention, the influence of the defect occurring in a first wiring layer is accommodated by forming a second wiring layer that has a function equivalent to the first wiring layer. When a defect exists in the first wiring layer, a defect occurs in a first insulating layer as a next layer to the first wiring layer. When the second wiring layer is formed, these defects are filled, therefore, the surface of the second wiring layer becomes flat. At this time, the first wiring layer and the second wiring layer are electrically connected to each other, so that the second wiring layer plays an electrical role the same as that of a wiring layer with no defect. Therefore, it is possible to prevent the influence of the defect upon a layer higher (the third wiring layer) than the second wiring layer, which allows yields to be improved.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.